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From: tim@hpfcla.UUCP
Newsgroups: net.micro
Subject: Re: what is the cpu for HP-87 ?
Message-ID: <10100009@hpfclp.UUCP>
Date: Tue, 21-Jan-86 18:12:00 EST
Article-I.D.: hpfclp.10100009
Posted: Tue Jan 21 18:12:00 1986
Date-Received: Thu, 13-Feb-86 21:28:46 EST
References: <1199@princeton.UUCP>
Organization: 21 Jan 86 16:12:00 MST
Lines: 47
The HP 85, 86 and 87 all use an HP proprietary processor. Having worked
on the 80 series I/O, I found it a nice processor.
It was designed for the 80 series desktop and a handheld product (a
derivative of which is the HP 75). Because of this background, low
power and few pins were a prime factor. The processor is an 8 bit in a
24 pin (?) package done originally in CMOS (but as I remember, the
production version was NMOS). It multiplexed data and address over 8
I/O lines. There was a address high and low strobe. Sequential
addresses did not require a new pair of address bytes, just a read or
write data strobe (the peripheral chips took care of incrementing their
address).
The processor has 64 8-bit registers. The first 32 of these are
addressable as 1 or 2 byte entities (byte or word). The second 32 of
these are addressable as 1, 2, 3, 4, 5, 6, 7 or 8 byte entities. The
way this works is through ARP (address register pointer) and DRP (data
register pointer) specifications (sort of a source/destination) and
through a single byte/ multibyte indication on the instruction. In the
following, the register numbers are in octal. I am a little fuzzy on
the 'syntax'. Some 'typical' sorts of assembly code looked like:
LDB R1,R2 single byte load from R2 into R1
LDM R0,R2 2 byte load from R2/R3 into R0/R1
BIN go into binary arithmetic mode
ADB R40,R50 add 1 byte R40 to R50 and put result in R50
ADM R40,R50 add 8 bytes R40-47 to R50-57, result in R50-57
(this is a 64 bit add)
ADM R44,R54 add 4 bytes
BCD go into decimal mode
ADM R40,R50 16 BCD digits R40-47,R50-57 result in R50-57
So the amount to be operated on depends on where you start. Outside of
these features, the CPU had normal sorts of operations. The 85 accessed
32K of RAM, 32K of ROM and some memory mapped I/O. The top 8K of ROM
was block switched for option ROMS. The 86 and 87 had block switched
RAM and supported up to 512K (I think). There is an assembler available
for the 80 series. There is also a Z80 CPM card available (I think only
for the 86/87).
As I remember, there was an HP Journal article on the processor (for the
85) in the July 1979 issue.
Tim Mikkelsen
hplabs!hpfcla!tim